1998,Peter JAshenden VHDL Quick Start.ppt

? 1998, Peter J. Ashenden VHDL Quick Start VHDL Quick Start Peter J. Ashenden The University of Adelaide Objective Quick introduction to VHDL basic language concepts basic design methodology Use The Student’s Guide to VHDLor The Designer’s Guide to VHDL self-learning for more depth reference for project work Modeling Digital Systems VHDL is for writing models of a system Reasons for modeling requirements specification documentation testing using simulation formal verification synthesis Goal most reliable design process, with minimum cost and time avoid design errors! Domains and Levels of Modeling Domains and Levels of Modeling Domains and Levels of Modeling Domains and Levels of Modeling Basic VHDL Concepts Interfaces Behavior Structure Test Benches Analysis, elaboration, simulation Synthesis Modeling Interfaces Entity declaration describes the input/output ports of a module VHDL-87 Omit entity at end of entity declaration Modeling Behavior Architecture body describes an implementation of an entity may be several per entity Behavioral architecture describes the algorithm performed by the module contains process statements, each containing sequential statements, including signal assignment statements and wait statements Behavior Example VHDL-87 Omit architecture at end of architecture body Omit is in process statement header Modeling Structure Structural architecture implements the module as a composition of subsystems contains signal declarations, for internal interconnections the entity ports are also treated as signals component instances instances of previously declared entity/architecture pairs port maps in component instances connect signals to component ports wait statements Structure Example Structure Example First declare D-latch and and-gate entities and architectures Structure Example Now use them to implement a register VHDL-87 Can’t directly instantiate entity/architecture pair Instead include component declarations in structural architecture body temp