VHDL的ASIC实现_后端程序.ppt

* * * * * * * * * * * * * 时间驱动（Timing Driven）布线 关键路径的布线优先进行 建立更短、更快的连接 验证 验证的目的和作用 Verification 形式验证（Formal Verification） 在时序优化和时钟树综合的时候，新的标准单元被加进来，还有的标准单元被替换。 Astro产生的最终网表（Post-Layout Netlist）需要和初始的门级网表(Pre-Layout Netlist)进行比对 形式验证（Formal verification）保证了设计在不同阶段的功能一致性（ functional equivalency ） 保证在后端设计中，用户想要的功能保持不变。 Formality? is the Sign-Off Tool for Formal Verification 时间验证 Star-RCXT? performs the layout parasitic extraction of the resistances and capacitances of all routes in the design Results in a format such as SPEF (Standard Parasitic Extended Format) SPEF is an smaller, extended format of Standard Parasitic Format (SPF), which enables the transfer of design specific resistances and capacitances from physical design to timing analysis and simulation tools Primetime? performs static timing analysis Detects timing violations by combining SPEF from Star-RCXT? and netlist from Astro? and checks against the design timing constraints (clock frequencies)Star-RCXT? and Primetime? are the Sign-Off Tools for Timing Verification 物理验证 Checks the design for fabrication feasibility and physical defects that could result in the design to not function properly 3 checks (DRC, ERC, and LVS) Design Rule Checks (DRC) Verifies that design does not violate any fabrication rules associated with the target process technology (metal width/space, antenna ratio, etc) Electrical Rules Checks (ERC) Verifies that there are no short or open circuits with power and ground as well as resistors/capacitors/transistors with floating nodes (part of LVS) Layout Versus Schematic (LVS) Final physical design matches the logical (schematic) version in terms of correct connectivity and number of electrical devices Hercules? is the Sign-Off Tool for Physical Verification 制造 Physical Design process is complete upon successful completion of timing, functional, and physical verification The design can be “Taped-Out” and GDSII created for the manufacturer GDSII (Graphic Design System II)