EECS3400_Lab12.docx

Lab ReportLab Assignment 12EECS 3400Electronics Lab IbyZhengkun YewithMarwan MohamedLaura MobulaApril 29, 2015IntroductionIn this lab students are required to build a PSPICE simulation to test and experiment with the BJT NAND circuit. Using collected data students should then be able to calculate the five characteristic points, the noise margins, logic swing, transition region, rise and fall times, and propagation delay of the NAND gate.Pre-LabFor the pre-lab students were required to write the PSPICE text code for the various tests required. This is shown in the appendix of the report as the circuit file.ProcedureMultiple tests are provided for the PSPICE analysis. Each of these tests are run separate from the others and include: varying both input voltages, holding one high and varying the other, and implementing a transient input. Each of these is included in the same circuit file and can be run be simply un-commenting the required instructions and commenting out the ones not required. Thus each test is conducted in order as provided in the lab assignment.TheoryThe first test run through PSPICE is the varying of both inputs. Since this is a NAND gate when both are a logical one the output should be low. AS both vary, once they both cross the threshold into VIL they will both be low and the output will be high. It should be noted here that there is no major differences between varying both or one of the inputs since the NAND gate is high whenever either one is low. In other words, all three characteristic graphs produced by the first three tests should be identical. Results of the three experiments are shown below in figures 1, 2, and 3.Figure 1: VTC when both inputs variedIn the attached images VA is represented by V2, VB by V3, Vo by V10 and V5 and V6 are the collector of Q1 and the base of Q3 respectively.Figure 2: VTC varying only AFigure 3: VTC varying only BWhat the above images show is that the NAND gate behaves essentially identical. However, the