常见面试笔试题-verilog程序库精选.docxVIP

加减法module addsub ( input [7:0] dataa, input [7:0] datab, input add_sub, // if this is 1, add; else subtract input clk, output reg [8:0] result); always @ (posedge clk) begin if (add_sub) result = dataa + datab; //or assign {cout,sum}=dataa+datab; else result = dataa - datab; end endmodule 四位的全加法器.module add4(cout,sum,a,b,cin)input[3:0]a,b;input cin;output [3:0] sum; output cout;assign {cout,sum}=a+b+cin;endmodule补码不仅可以执行正值和负值转换，其实补码存在的意义，就是避免计算机去做减法的操作。　　1101 -3 补+ 1000 8 01015假设 -3 + 8，只要将 -3 转为补码形式，亦即 0011 = 1101，然后和 8，亦即 1000 相加就会得到 5，亦即 0101。至于溢出的最高位可以无视掉。乘法器module mult(outcome,a,b);parameter SIZE=8;input[SIZE:1] a,b;output reg[2*SIZE:1] outcome;integer i;always @(a or b) begin outcome=0; for(i=0,i=SIZE;i=i+1) if(b[i]) outcome=outcome+(a(i-1)); endendmodule另一种乘法器。在初始化之际，取乘数和被乘数的正负关系，然后取被乘数和乘数的正值。输出结果根据正负关系取得。else if( Start_Sig ) case( i ) 0: begin isNeg = Multiplicand[7] ^ Multiplier[7]; Mcand = Multiplicand[7] ? ( ~Multiplicand + 1b1 ) : Multiplicand; Mer = Multiplier[7] ? ( ~Multiplier + 1b1 ) : Multiplier; Temp = 16d0; i = i + 1b1; end 1: // Multipling if( Mer == 0 ) i = i + 1b1; else begin Temp = Temp + Mcand; Mer = Mer - 1b1; end 2: begin isDone = 1b1; i = i + 1b1; end 3: begin isDone = 1b0; i = 2d0; end endcase assign Done_Sig = isDone; assign Product = isNeg ? ( ~Temp + 1b1 ) : Temp; endmodule booth乘法器module booth_multiplier_module( input CLK, input RSTn, input Start_Sig, input [7:0]A, i