组合逻辑电路和设计试题.pptVIP

* * * * * * * * * * NOR Gate as an Inverter The NOR Gate as a Universal Logic Element Two NOR Gates as an OR Gate Three NOR Gates as an AND Gate Four NOR Gates as an NAND Gate NAND logic for X = AB + CD ? 5-4 COMBINATIONAL LOGIC USING NAND AND NOR GATE DeMorgan’s 最简逻辑电路标准 门的个数最少 每个门的连线最少 门的种类最少  NAND Logic Diagrams Using Dual symbols when drawing a NAND logic diagram, always use the gate symbols in such a way that every connection between a gate output and a gate input is either bubble-to-bubble or nonbubble-to-nonbubble. Use of the appropriate dual symbols in a NAND logic diagram every connection between a gate output and a gate input is either bubble-to-bubble or nonbubble-to-nonbubble EXAMPLE : Implement each expression with NAND logic using appropriate dual symbols (a) EXAMPLE : Implement each expression with NAND logic using appropriate dual symbols (b) NOR LOGIC NOR negative-AND NOR logic for X = (A + B)(C + D) A NOR gate function as either a NOR or a negative-AND. 180 三人表决电路: Implement a voting circuit for three person(A、B、C): Use NAND gates A B C And-Or Logic Gates A B C NAND Logic Gates 最简逻辑电路标准 门的个数最少 每个门的连线最少 门的种类最少 Implement a three inputs parity checker: The output is “1” when the number of input “1” is odd. 奇偶检验器 (3) Convert to NAND logic (2) Logic expression Use NAND Gates! EX 5-12： Determine the final output waveform X for the circuit, with input waveforms A,B and C as shown. 5-5 CIRCUIT OPERATION WITH PULSE WAVEFORM INPUTS EX 5-11： Draw the timing diagram Find out the logic circuit that will generate the output waveform for the inputs. inputs output A B C X 0 0 0 Page193: Problem30 Homework : Page193 Problem31 Digital System Application 7-segment displays page149 共阳极接法 共阴极接法 g f e d c b a 例： 共阴极接法 a b c d e f g 0 1 1 0 0 0 0 1 1 0 1 1 0 1 低电平时发光 高电平时发光 共阳极接法 a b c g d e f + d g f e c b a g 共阴极接法 a b c d e f g 二－十进制编码 ? 显示器件 D C B A a b c d e f g 0 0 0 0