ppt课件-self-alignedsilicideprocess-eecsinstructionalsupport.pptVIP

* Professor N Cheung, U.C. Berkeley Lecture 19 EE143 F2010 V DD GND Select mask (dark field clear field) P-well mask (dark field) Note body contacts: p-well to GND n-substrate to VDD CMOS Inverter Layout PMOS W/L=9l/2l NMOS W/L=3l/2l Active (clear field) Gate (clear field) Contact (dark field) Metal (clear field) Visualizing Layouts and Cross-Sections with SIMPLer SIMPL is a CAD tool created by Prof. Neureuther’s group allows IC designers to visualize device cross-sections corresponding to a fabrication process and physical layout. A Berkeley undergraduate student, Harlan Hile, cr