Macro 的Synthesis Guidelines.pptVIP

Discussing the strategies for developing macro synthesis scripts that enable the integrator to synthesize the macro and meet timing goals Outline Overview of the synthesis problem Macro synthesis strategy High-performance synthesis RAM and data-path generators Coding guidelines for synthesis scripts Outline Overview of the synthesis problem Macro synthesis strategy High-performance synthesis RAM and data-path generators Coding guidelines for synthesis scripts Overview of the synthesis problem Special problems with synthesis of parameterizable soft macros Must allow the integrator to synthesize the macro and meeting the timing goals in the final chip Must meet timing with different cell libraries of integrators Must meet timing with different configurations of the macro Overview of the synthesis problem Each synthesizable unit or module in the design has a timing budget Each module meets the timing budget, the macro is ensured of meeting its overall timing goals Synthesis problems become localized Difficult problems can be solved on small modules Outline Overview of the synthesis problem Macro synthesis strategy High-performance synthesis RAM and data-path generators Coding guidelines for synthesis scripts Macro synthesis strategy Goal To develop a set of constrains for the macro early in the design process and to use the bottom-up synthesis strategy Key points Macro timing budget Subblock timing budget Synthesis in the design process Subblock synthesis process Macro synthesis process Wire load models Preserve clock and reset networks Code checking Macro timing budget The macro timing budget must specify Clock definition Setup time requirements Clock to output delay requirements Input and output delays for all combinational paths Loading budget for outputs and driving cell for inputs Operating conditions Temperature Voltage …. Subblock timing budget The subblock timing budget must specify Clock definition Setup time requirements Clock to output delay requirement