FIR滤波器VHDL实验报告.docxVIP

EDA技术及应用实 验 报 告FIR滤波器的设计 学生姓名张志 翔班级电子信息工程1203班学号12401720522指导教师 2015.5.9FIR滤波器的设计1.实验目的（1）学习VHDL语言的综合设计应用（2）学习设计FIR滤波器2.实验内容根据如图所示的转置FIR滤波器原理设计一个长度为4的DaubechiesDB4转置FIR滤波器的设计。3.实验条件（1）开发软件：Quartus II 8.0。 （2）实验设备：GW48-CK EDA实验开发系统。 （3）拟用芯片：EP3C55F484C84.实验设计1）VHDL源程序LIBRARY LPM;USE LPM.LPM_COMPONENTS.ALL;LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY FIR IS GENERIC(W1:INTEGER:=9; W2:INTEGER:=18; W3:INTEGER:=19; W4:INTEGER:=11; L:INTEGER:=4; MPIPE:INTEGER:=3); PORT(CLK:IN STD_LOGIC; LOAD_X:IN STD_LOGIC; X_IN:IN STD_LOGIC_VECTOR(W1-1 DOWNTO 0); C_IN:IN STD_LOGIC_VECTOR(W1-1 DOWNTO 0); Y_OUT:OUT STD_LOGIC_VECTOR(W4-1 DOWNTO 0));END ENTITY FIR;ARCHITECTURE ART OF FIR IS SUBTYPE N1BIT IS STD_LOGIC_VECTOR(W1-1 DOWNTO 0); SUBTYPE N2BIT IS STD_LOGIC_VECTOR(W2-1 DOWNTO 0); SUBTYPE N3BIT IS STD_LOGIC_VECTOR(W3-1 DOWNTO 0); TYPE ARRAY_N1BIT IS ARRAY (0 TO L-1) OF N1BIT; TYPE ARRAY_N2BIT IS ARRAY (0 TO L-1) OF N2BIT; TYPE ARRAY_N3BIT IS ARRAY (0 TO L-1) OF N3BIT; SIGNAL X:N1BIT; SIGNAL Y:N3BIT; SIGNAL C:ARRAY_N1BIT; SIGNAL P:ARRAY_N2BIT; SIGNAL A:ARRAY_N3BIT; BEGIN LOAD:PROCESS IS BEGIN WAIT UNTIL CLK=1; IF(LOAD_X=0) THEN C(L-1)=C_IN; FOR I IN L-2 DOWNTO 0 LOOP C(I)=C(I+1); END LOOP; ELSE X=X_IN; END IF; END PROCESS LOAD; SOP:PROCESS(CLK) IS BEGIN IF CLKEVENT AND (CLK=1) THEN FOR I IN 0 TO L-2 LOOP A(I)=(P(I)(W2-1)P(I))+A(I+1); END LOOP; A(L-1)=P(L-1)(W2-1)P(L-1); END IF; Y=A(0); END PROCESS SOP; MULGEN:FOR I IN 0 TO L-1 GENERATE MULS:LPM_MULT GENERIC MAP(LPM_WIDTHA=W1,LPM_WIDTHB=W1, LPM_PIPELINE=MPIPE, LPM_REPRESENTATION=SIGNED, LPM_WIDTHP=W2, LPM_WIDTHS=W2) PORT MAP(CLOCK=CLK,DATAA=X,DATAB=C(I),RESULT=P(I));END GENERATE;Y_OUT=Y(W3-1 DOWNTO W3-W4);END ARCHITECTURE ART;2）仿真结果验证使用quartus对FIR进行时序仿真的结果当输入数据为X_IN(0) X_IN(1) X_IN(2) X_IN(3) X_IN(4)分别为100 150 200 250 60 140 180则输出 Y_OUT(0) Y_OUT(1) Y_OUT(2) Y_OUT(3) Y_OUT(4) 应该是Y_OUT(0)=[124*X_IN(0)+214*X_IN(1)+57*X_IN(-2)-33*X_IN(-3) =48…….可以看出，仿真结果是正确的3）逻辑综合分析5.实验总结很好地