Cadenc and the Future of EDA.pptVIP

Cadence and the Future of EDA Paul McLellan paulmcl@ Consumerization of Electronics Turning Up the Heat on Design Consumer markets hard to predict, forcing shorterand shorter design cycles time-to-market even more important Cost pressures intense productivity even more important Designer shortage productivity even more important Product life-cycles shorter cost of design must be recovered over shorter time Semiconductor physics continues to get more difficult second-order effects become first-order Economics of Chip Design To make money, a chip must recover the cost of getting to manufacture over its life high volume or high margin High margin depends on differentiation very high complexity digital (“anyone” can do low complexity digital) analog complex software process technology High volume depends on aggregation or a high-volume application (e.g. cell-phones) aggregation through FPGAs aggregation through platform-based design Time to Get New EDA TechnologyInto Designers’ Hands Is Too Long Improving productivity for faster time-to-market isdriving change Increased importance of embedding methodology within tools Increased importance of ‘true’ integration Complexity of chips drives the need for prescriptivesolutions to problems Simply identifying problems, i.e. 0.1% or 10,000 nets have problems, which require manual fixing is useless. Analysis must be embedded within the implementation tools Landscape Continues to Change 80% of chips will be mixed-signal Shortage of analog designers continues to worsen future tools will need to vastly improve productivity of the relatively small design force Semiconductor processes continue to scale (Moore’s law) Timing closure, signal integrity closure, design closure Design methodologies will have to abstract upwards Platform-based design or IP-based design The basic infrastructure will have to change Databases too huge to pass via files Semantic inconsistencies between tools lead to non-convergence Solutions Must be Dr