ASSURArcx extraction solution.pptVIP

DAC 2001 Custom IC Solutions Assura RCX Value Physical Verification in Custom IC Flow Best-in-Class Extraction Solution Superior Accuracy Assura RCX Performance Capacity Tight Integration Provides Highest Productivity Complete front-to-back integration with the industry’s most widely used Analog Design Environment Familiar Diva use model Easy adoption into existing design flows Quick assessment and optimization of layout parasitics: Backannotation of lumped R C values on the schematic View parasitics on individual nets Do cross-probing of parasitics See coupling parasitics between nets Perform post-extraction filtering for parasitic reduction Parasitic simulation debug from the schematic Assura RCX-FS (3.0 Option) Superfast 3D field solver practical for full-chip extraction 10-70X faster than QuickCap for comparable accuracy Lucent technology (Nebula) exclusively licensed to Cadence Used successfully for RF and opto-electronics chips at Lucent Uncompromising capacitance extraction accuracy Reference level accuracy Standard deviation: 1% Seamless integration with Assura RCX Can be used for entire block or critical net (path) extraction Intelligent handling of extraction at RCX/RCX-FS boundaries RCX/RCX-FS results are merged for re-simulation Assura RCX-FS: Critical Net Extraction Powerful combination for highest accuracy and highest speed parasitic extraction Use Assura RCX-FS for critical net extraction Surrounding nets included in data tube Use Assura RCX for the rest of the chip Automatic merging of results from RCX-FS critical net extraction and full-chip RCX extraction results Reference Level Accuracy Inductance Extraction (3.0 Option) Full chip-level RLC extraction solution Optimized speed and accuracy with partitioning and filtering mechanisms Extracts both self and mutual inductance First in the industry to provide full-chip mutual inductance capability Mutual inductance important for SI analysis No need for user-specified return paths Integration