Moore时序电路设计陆海雷200713010907电子班.docVIP

深 圳 大 学 实 验 报 告 课程名称： 数字系统设计 实验项目名称： Moore时序电路设计 学院： 信息工程学院 专业： 电子信息工程 指导教师： 梁松海 报告人：陆海雷 学号：2007130109 班级： 07电1 实验时间： 实验报告提交时间： 2009.10.20 教务处制 一．费归零码-曼彻斯特码转换器程序代码 -------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 19:59:31 10/20/09 -- Design Name: -- Module Name: moore01 - Behavioral -- Project Name: -- Target Device: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- -------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity moore01 is port(x:in std_logic; clk,rst:in std_logic; z:out std_logic); end moore01; architecture Behavioral of moore01 is type state is (s0,s1,s2,s3); signal p_state, n_state:state; begin process(rst,clk) begin if(rst=1)then p_state =s0; elsif(clk event and clk =1)then p_state=n_state; end if; end process; process(p_state,x) begin case p_state is when s0 = z=0; if x=0then n_state =s1; else n_state=s3; end if; when s1 = z=0; if x=0then n_state =s2; end if; when s2 = z=1; if x=0then n_state =s1; else n_state=s3; end if; when s3 = z=1; if x=1then n_state =s0; end if; end case; end process; end Beh