Memory April , 培训讲义.pptVIP

Virtual MemoryApril 3, 2001 Topics Motivations for VM Address translation Accelerating translation with TLBs Motivations for Virtual Memory Use Physical DRAM as a Cache for the Disk Address space of a process can exceed physical memory size Sum of address spaces of multiple processes can exceed physical memory Simplify Memory Management Multiple processes resident in main memory. Each process with its own address space Only “active” code and data is actually in memory Allocate more memory to process as needed. Provide Protection One process can’t interfere with another. because they operate in different address spaces. User process cannot access privileged information different sections of address spaces have different permissions. Motivation #1: DRAM a “Cache” for Disk Full address space is quite large: 32-bit addresses: ~4,000,000,000 (4 billion) bytes 64-bit addresses: ~16,000,000,000,000,000,000 (16 quintillion) bytes Disk storage is ~170X cheaper than DRAM storage 20 GB of DRAM: ~ $20,000 20 GB of disk: ~ $120 To access large amounts of data in a cost-effective manner, the bulk of the data must be stored on disk Levels in Memory Hierarchy DRAM vs. SRAM as a “Cache” DRAM vs. disk is more extreme than SRAM vs. DRAM Access latencies: DRAM ~10X slower than SRAM Disk ~100,000X slower than DRAM Importance of exploiting spatial locality: First byte is ~100,000X slower than successive bytes on disk vs. ~4X improvement for mode vs. regular accesses to DRAM Bottom line: Design decisions made for DRAM caches driven by enormous cost of misses Impact of These Properties on Design If DRAM was to be organized similar to an SRAM cache, how would we set the following design parameters? Line size? Associativity? Write through or write back? What should the impact of these choices be on: miss rate hit time miss latency tag storage overhead Locating an Object in a “Cache” SRAM Cache Tag stored with cache line Maps from cache block to me