Source Card Design Status and Plans培训教程文件.pptVIP

18.01.06 J. Jones (Imperial College London), Alt. GCT Mini-Meeting Source Card Design Status and Plans Overview Source Card Tasks Separate e/γ from jets Condense 2x68-way SCSI (RCT) ? 4x1.4Gbit/s optical fibre BC0 sync. checking (compare TTC with BC0 embedded in data) Autocalibrated delay to phase match data on different channels (if required) USB 2.0 interface for diagnostic/testing (borrowed from IDAQ-APVE) Swtiches data between channels to provide ‘split’ information to leaf cards Extra features On-board temperature/status monitoring Read out either during gaps in data (via concentrator card)…or via USB Data capture from RCT (for debugging) Internal test pattern generation (up to 1024BX) for testing leaf cards, etc… Can (in theory) scale to 2 x required bandwidth (pin-compatible part) Board Layout (Preliminary) 6/8-layer 6U VME form factor USB 2.0 (Cypress SX2) TTCrx QPLL 2xVHDCI SCSI for RCT input 4xOptical SFP output SerDes Linear supplies for fast components Switch-mode (TI) for logic Either: 2 x XC3S1000-4FT256 (~￡80) Simpler design Longer latency Or: 1 x Xilinx Spartan 3 4-8 x Xilinx Coolrunner-II CPLD More complex design Lower Latency Functional Issues (To Be Discussed) Clock Distribution Direct from QPLL Split by dedicated clock buffer (made by TI) No PLL in splitter to minimise jitter Max skew ~500ps (OK for 80MHz) SerDes TLK2501 seems like a good choice with bandwidth margin ECL Termination Scheme Have a version done, but would like to discuss with Wisconsin first Similar to Bristol IM, with a few extra tweaks / options Use same buffers (they have wide common-mode range, +5V to -4V) Source Card Latency RCT-Leaf (Maximum Limit) Madison Cable (quoted from datasheet) 1.5ns/ft Assume 5ft max. length = 1.5x5 = 7.5ns delay ECL Buffers 2.5ns-6ns (4ns typical) FPGA/CPLD FPGA (XC3S1000): 5ns in IOBs, at a guess 5ns trace delay = 10ns CPLD (Coolrunner-II): 3.8ns-7.1ns total delay SerDes 38 bit-times@1.6GHz (625ps) = 23.75ns PCB Tracking Assume 10