现代CMOS工艺基本流程(英文)演示文件修改版.pptVIP

* 2nd through Nth Interconnect Layer Pattern Photoresist for Metal2 Interconnects: Adjacent metal layers are patterned perpendicular to each other to minimize inductive coupling between layers (not shown in cross-sectional diagram). Silicon Substrate P+ Silicon Epi Layer P- P- Well N- Well N+ Source N+ Drain P+ Source P+ Drain BPSG W Contact Plug Metal1 IMD1 W Via Plug Metal2 Photoresist * 2nd through Nth Interconnect Layer Etch Metal2: An RIE etch utilizing chlorine chemistry. Multiple etch steps are required due to the multiple different metal layers. Silicon Substrate P+ Sili