基于OMAP平台的硬件设计规则干货.docxVIP

上电时序The device should be powered-on in the following order:1) RTC (RTC_CVDD) may be powered from an external device (such as a battery) prior to all othersupplies being applied. If the RTC is not used, RTC_CVDD should be connected to CVDD.?2a) All variable 1.2V - 1.0V core logic supplies (CVDD)?2b) All static 1.2V logic supplies (RVDD, VDDA_12_PLL0, VDDA_12_PLL1, USB_CVDD,SATA_VDD). If voltage scaling is not used on the device, groups 2a) and 2b) can be controlled fromthe same power supply and powered up together.?3) All static 1.8V IO supplies (DVDD18, DDR_DVDD18, USB0_VDDA18, USB1_VDDA18 andSATA_VDDR) and any of the LVCMOS IO supply groups used at 1.8V nominal (DVDD3318_A,DVDD3318_B, or DVDD3318_C).4) All analog 3.3V PHY supplies (USB0_VDDA33 and USB1_VDDA33; these are not required if bothUSB0 and USB1 are not used) and any of the LVCMOS IO supply groups used at 3.3V nominal(DVDD3318_A, DVDD3318_B, or DVDD3318_C).There is no specific required voltage ramp rate for any of the supplies as long as the LVCMOS suppliesoperated at 3.3V (DVDD3318_A, DVDD3318_B, or DVDD3318_C) never exceed the STATIC 1.8Vsupplies by more than 2 volts.通过控制电源芯片的各个模块的时能来控制OMAPL138的上电时序。FLASH连接采用128M NAND FLASH进行连接DDR连接OMAP L138内存控制器支持以下类型：· JESD79D-2A standard compliant DDR2 SDRAM· Mobile DDR SDRAM· 512 MByte memory space for DDR2· 256 MByte memory space for mDDR· CAS latencies:– DDR2: 2, 3, 4 and 5–mDDR: 2 and 3· Internal banks:– DDR2: 1, 2, 4 and 8– mDDR:1, 2 and 4· Burst length: 8· Burst type: sequential· 1 chip select (CS) signal· Page sizes: 256, 512, 1024 and 2048· SDRAM autoinitialization· Self-refresh mode· Partial array self-refresh (for mDDR)· Power down mode· Prioritized refresh· Programmable refresh rate and backlog counter· Programmable timing parameters· Little endianDDR采用专用接口，布线要求如上图所示。晶振的设计晶宇星科技的晶振电路晶体振荡器的频率会随着外部负载电容变化，因此在许多频率中使用了变频二极管设计，已获得不同的频率。负载电容CL=（CG×CD）/(CG+CD)+杂散电容+IC中电容杂散电容和布局布线有关，一般为几pF。负载电容小于晶振选型要求的电容时，晶振的频率会增高。TPS65070供电设计TPS65070可以采用默认的上电顺序启动。具体使用在以后DEEPSLEEP研究阶