基于精英池演化算法的数字电路在片演化方法.docVIP

基于精英池演化算法的数字电路在片演化方法( 何国良1,2　李元香1,2 史忠植3 1武汉大学软件工程国家重点实验室 武汉　430072 2武汉大学计算机学院　武汉　430072 3中国科学院计算技术研究所智能信息处理重点实验室　北京　100190 摘要：２０世纪末演化硬件技术的提出，为实现硬件系统的自适应与智能化等特征提供了一种可行的新技术，现阶段电路进化是演化硬件研究的热点之一。本文引入人工经验与规则，提出一种扩展矩阵编码法，保护具有较优结构的电路个体不易淘汰；其次，基于多目标和局部寻优技术，结合子电路杂交与单元重要性的自适应变异策略，提出了一种设计数字电路的精英池演化算法，并在可编程逻辑器件上实现电路的自主动态重构与评价等演化过程。 关键词：演化硬件　演化算法　电路演化　在片演化 中图分类号： TP302 Elitist Pool Evolutionary Algorithm for on-line evolution of digital circuits HE Guo-Liang1,2 LI Yuan-Xiang1,2 SHI Zhong-Zhi3 1 State Key Laboratory of Software Engineering, Wuhan University, Wuhan, 430072 2 College of Computer Science, Wuhan University, Wuhan, 430072 3 Key Laboratory of Intelligent Information Processing, Institute of Computing Technology, Beijin 100190 Abstract: Evolvable hardware (EHW) refers to reconfiguration hardware design with natural algorithms, which could change its architecture and behavior dynamically and autonomously by interacting with its environment. At present, the auto-design of electronic and analog circuits is a one of hot issues in the field of EHW. In this paper, an elitist pool evolutionary algorithm (EPEA) with some evolution techniques is proposed to optimize the evolutionary design of logic circuits efficiently. First, an extended matrix encoding method is proposed based on human experiences and principles to increase the fitness value of some evolved circuits quickly. This representation can be expected to reflect the potential performance of circuits and avoid deleting some inferior circuits with a good developing potential during the evolution. Then, a novel sub-circuit crossover operator and an adaptive mutation strategy are introduced to improve design efficiency in terms of the techniques of the multi-objective and local searching optimization. Moreover, a framework of on-line evolution is employed to implement EPEA on field-programmable gate array (FPGA). Experiments show that the proposed methods can design digital circuits automatically and