VerilogHDL实验内容.ppt

第七章 逻辑电路的描述 7．1 组合电路的设计 7．2 时序电路的设计 7．3 有限状态机 7. 4 存储器的描述 7．1 组合电路的设计 7.1.1 3线-8线译码器 module decoder(out,in); output[7:0] out; input[2:0] in; reg[7:0] out; always@(in) begin … end endmodule 7.1.2 8线-3线编码器 module zcoder(out,in); output[2:0] out; input[7:0] in; reg[2:0] out; always@(in) begin … end endmodule 7.1.3 七段显示译码器 BCD-七段显示译码电路的真值表 case({D3,D2,D1,D0}) 4d0: {a,b,c,d,e,f,g}=7b1111110; 4d1: {a,b,c,d,e,f,g}=7b0110000; 4d2: {a,b,c,d,e,f,g}=7b1101101; 4d3: {a,b,c,d,e,f,g}=7b1111001; 4d4: {a,b,c,d,e,f,g}=7b0110011; 4d5: {a,b,c,d,e,f,g}=7b1011011; 4d6: {a,b,c,d,e,f,g}=7b1011111; 4d7: {a,b,c,d,e,f,g}=7b1110000; 4d8: {a,b,c,d,e,f,g}=7b1111111; 4d9: {a,b,c,d,e,f,g}=7b1111011; default: {a,b,c,d,e,f,g}=7bx; endcase 7．1 .4 四选一数据选择器 module mux_case(out,in0,in1,in2,in3,sel); output out; input in0, in1, in2, in3; Input [1:0] sel; reg out; always @(in0 or in1 or in2 or in3 or sel) begin case(sel) 2b00: out=in0; 2b01: out=in1; 2b10: out=in2; default: out=in3; endcase end endmodule module mux_if(out,in0,in1,in2,in3,sel); output out; input in0,in1,in2,in3; input[1:0] sel; reg out; always @(in0 or in1 or in2 or in3 or sel) begin if(sel= =2b00) out=in0; else if(sel= =2b01) out=in1; else if(sel= =2b10) out=in2; else out=in3; end endmodule 7.1.5 数据分配器 module zss_if(out0, out1, out2, out3, in0,sel); output out0, out1, out2, out3; input in0; input[1:0] sel; reg out; always @(in0 or sel) begin {out0, out1, out2, out3} = 4’b0000; if(sel= =2b00) out0=in0; else if(sel= =2b01) out1=in0; else if(sel= =2b10) out2=in0; else if(sel= =2b11) out3=in0; end endmodule 7．1 .5 数据比较器 7．2 时序电路的设计 7.2.1 D触发器 异步清0，异步置1 module DFF1(q,qn,d,clk,set,reset); input d,clk,set,reset; output q,qn; reg q,qn; always @(posedge clk or negedge set or negedge reset) begin … end endmodule 同步清0，同步置1 if (reset) begin q = 0; qn = 1; end else if (set) begin q