基于FPGA的信号发生器翻译.docVIP

Reconfigurable Readback-Signal Generator Based on a Field-Programmable Gate Array Jinghuan Chen, Jaekyun Moon, and Kia Bazargan, Member, IEEE Abstract—We have designed a readback-signal generator to provide noise-corrupted signals to a read channel simulator. It is implemented in a Xilinx Virtex-E field-programmable gate array (FPGA) device. The generator simulates in hardware the noise processes and distortions observed in hard drives. It uses embedded nonuniform random number generators to simulate the random characteristics of various disturbances in the read/write process. The signal generator can simulate readback pulses, intersymbol interference, transition noise, electronics noise, head and media nonlinearity, intertrack interference, and write timing error according to the characteristics specified by the user. A sample implementation operates at a 70-MHz clock speed. The design can easily be scaled for different error rates. The generator can be reconfigured in real time to give the user flexibility and increase the capacity of the FPGA device. The readback-signal generator can be integrated into an FPGA read channel simulator or serve as a test bench for data-recovery circuits. Index Terms—Field programmable gate array (FPGA), Gaussian pseudorandom number generator, magnetic recording, read channel, read channel modeling, reconfigurable computing, transition noise. I. INTRODUCTION INTENSIVE simulation is often carried out to investigate advanced signal processing techniques for data storage applications. The simulation is normally performed in software that may take a very long time. For instance, the simulation of a 10 bit-error rate (BER), assuming 10 bit errors are observed, can take days running on a personal computer equipped with a 1-GHz Pentium IV processor. On the other hand, the target sector retry rates [i.e., unrecoverable error rates after error-correction- code (ECC)] in commercial hard drives normally go below 10 for desktop products and 10 f