Design_Spec_template【DOC精选】.docVIP

I. Functional Description (Algorithm overview and description; missions and tasks of the module) II. Module Micro-architecture (A very detailed section; put as many details as possible; should be a heavy section) (A) Design Requirements (B) Block Diagrams and Description (Block diagram – in hierarchical form for complicate designs) (Describe what each block does; and the thoughts how and why it is micro-architected so) (C) State Machine Diagram and description (Major state diagrams in your design, and describe/explain the states and branch conditions associated with them) III. Register Map (A) Address Range (B) Register Description IV. File Structure and Module Hierarchy (Tabulate modules in each .v file and sub-smodule dependency for module hierarchy.) (Brief description of each module – what the module does.) V. Top I/O Ports and Description (A) Inputs (Input pins including bit width and brief description) (B) Outputs (Output pins including bit width and brief description) VI. Macrocell List and Flip-Flop Registers (A list of all SRAM, RF, ROM cells, including information pertinent to the cells) (A list of all IPs licensed from outside, including information pertinent to the IPs) (Total number of flip-flop registers in each clock domain) VII. Timing Diagram VIII. Functional Verification (How is the test bench set up? – including how to clone external components used with your design in verification) (What test cases need be verified? Description of test cases and verification status) (What is supposed to be verified and is not verified? Why?) IX. Performance Related (For example, how many cycles to process I, P, B frames? …. etc.) (Clock requirements: how fast is the clock?) (Combinational, noncombinational, memory area report from synthesis – including synthesis library and environment setup) Appendix A: Asynchronous design (if applicable) Appendix B: Built-in test logic (if applicable) Example I.