VHDL程序集锦.docVIP

组合逻辑：-- Highest Priority Encoder -- download from LIBRARY ieee; USE ieee.std_logic_1164.ALL; entity priority is port(I : in bit_vector(7 downto 0); --inputs to be prioritised A : out bit_vector(2 downto 0); --encoded output GS : out bit); --group signal output end priority; architecture v1 of priority is begin process(I) begin GS = 1; --set default outputs A = 000; if I(7) = 1 then A = 111; elsif I(6) = 1 then A = 110;