0.15μm低压制程漏电流及通孔电阻降低.pdf

0.15 μm 低压制程漏电流及通孔电阻的降低 摘 要 0.15μm 低压制程是在0.15μm 标准制程的基础上衍生出来的一种特 殊制程。它利用光学邻近矫正技术把晶体管的线宽从 0.15μm 修正为 0.13μm 而同时长度保持不变，以期提高晶体管的速度。 在实际生产中我们在浅沟道隔离(STI) 的拐角位置发现了缺角 (divot)，它与覆盖在上面的多晶硅构成了寄生晶体管，从而增加了静态 漏电流。通过加大STI 与衬底的垂直角度，我们降低了STI 化学机械研 磨过程中产生的机械应力，同时缩短湿法清洗去除pad oxide 的时间来 减轻divot 的形成，降低寄生漏电流。另外我们在STI liner oxide 之后增 加了一层SiN，进一步降低了漏电流。 生产中遇到的另一个问题就是过高的通孔电阻会导致扫描链功能 性失效。经过分析我们通过缩短via 过度蚀刻时间的方法，避免了由于 阻挡层被完全穿透引起的铝金属挤进via 内部的现象，降低了通孔的接 触电阻，减少了因RC 延迟效应带来的扫描链功能性失效。 经过这些工艺优化，我们解决了漏电流问题和扫描链功能性失效问 题带来的良率损失，将产品的良率从70 ％提升到90 ％。 关键词： 漏电流，浅沟道隔离，通孔电阻，良率提升 LEAKAGE AND VIA RESISTANCE REDUCTION FOR 0.15UM LOW VOLTAGE PROCESS ABSTRACT 0.15μm low voltage process is a kind of special process come from 0.15 μm general process. After optical proximity correction, the width of gate has been changed to 0.13μm from 0.15μm, and keeps the original length to improve the device performance. During the production we found divot on the top corner of STI. It will become autoecious transistor after poly deposition and bring extra leakage. Through enlarging the STI etch angle, we decreased the stress from STI CMP process, and reduced the wet clean time used for pad oxide removing to prevent divot. And we also added one SiN layer after STI liner oxide to reduce the STI leakage continuously. Another problem was the high via resistance would cause scan function fail. We reduced via over etching time to prevent stop layer been etched through, which could lead metal extrusion and increase via resistance. This action could reduce the scan function failure because of RC delay. After the process optimization, we solved the leakage issue a