符号化模拟电路仿真器的实现与应用-CECS.doc

申请上海交通大学工学硕士学位论文 符号化模拟电路仿真器的实现与应用 学 校： 上海交通大学 院 系： 微电子学院 班 级： B0421091 学 号： 1042109028 姓 名： 陈微微 专业方向： 计算机系统结构 学 科： 工学 施国勇教授 导 师： 付宇卓教授 答辩日期： 2007年1月19日 上海交通大学微电子学院 2007年1月 A Dissertation Submitted to Shanghai Jiao Tong University for Master Degree of Science A Symbolic Analog Circuit Simulator Author：CHEN, Weiwei Major: Computer Architecture Advisor Ⅰ: Prof. SHI, Guoyong Advisor Ⅱ: Prof. FU, Yuzhuo School of Microelectronics Shanghai Jiao Tong University Shanghai, P.R.China January, 2007 摘 要 本文论述了一个基于拓扑方法的符号化模拟电路仿真器。该仿真器基于一种全新的拓扑网络分析算法，通过电路子图约化的方式，建立表达电路生成项的二分判定图。通过子图和节点共享以及二分判定图的相关操作，获得理想的电路分析的时间和空间复杂度。 本文第一章和第二章首先介绍符号化分析方法，然后提出一组基于拓扑法的电路分析定理，第三章中具体介绍仿真器的实现，第四章报告了实验的分析结果，第五章讨论了符号化的近似分析方法，最后对全文进行总结和展望。 本文提出的仿真器是目前第一个可以成功地通过拓扑方法分析较大规模模拟测试电路(20 – 30个传输晶体管)的符号化模拟电路仿真器。 关键词：符号化分析、二分判定图、图约化、启发式排序 ABSTRACT Many topological approaches to symbolic network analysis have been proposed in the literature, but none are implemented ultimately as a simulator for large network analysis due to their complexity and exponentially increasing number of terms. A novel methodology adopted in this paper uses a graph reduction approach based on a set of graph reduction rules developed recently. A Binary Decision Diagram (BDD) is used in the implementation of the symbolic circuit simulator described in this thesis. With sharing and other manipulations of BDD, high simulation and evaluation performance is achieved. The thesis is organized as follows. A brief introduction to symbolic analysis is in Chapter 1. The graph reduction rules and corresponding algorithms are presented in Chapter 2. Implementation details on the symbolic simulator are discussed in Chapter 3. Experimental results are reported in Chapter 4. In Chapter 5, approximate circuit analysis approaches are introduced. Conclusions and future work are reported in Chapter 6. The simulator in this thesis is