Increasing Hardware Efficiency with Multifunction Loop多功能循环提高硬件效率.pptVIP

Streamroller: Compiler Orchestrated Synthesis of Accelerator Pipelines Manjunath Kudlur, Kevin Fan, Ganesh Dasika, and Scott Mahlke University of Michigan Automated C to Gates Solution SoC design 10-100 Gops, 200 mW power budget Low level tools ineffective Automated accelerator synthesis for whole application Correct by construction Increase designer productivity Faster time to market Streaming Applications Data “streaming” through kernels Kernels are tight loops FIR, Viterbi, DCT Coarse grain dataflow between kernels Sub-blocks of images, network packets System Schema Overview Input Specifica