TIPP(aoyagi)v3-e.ppt-CERNIndico.ppt

* * * * * * * * Cross sectional TEM imageof multilayer nanofilms 10μm Wafer Si:5nm C:7nm Si:5nm C:7nm ??? Si buffer layer:20nm Si:5nm C:7nm Si:5nm C:7nm ??? Si Buffer layer:20nm Si:5nm C:7nm Si:5nm C:7nm ??? Si:5nm A Structure (Thickness ：492nm) B Structure　18cycle B Structure(thickness ：507nm) Multilayer Nanofilm Stack Raman spectroscopic analysis FWHM of G-peak :119cm-1 *FWHM of G-peak at single carbon layer: 112cm-1 → The thermal conductivity of multilayer nanofilms is 800~1000W/mK Crystallinity of multilayer nanofilms Micro heater device Chip size : 3×3mm Heater size 1×1mm Ambient temp.: 23?C Heating value: 0.1W Transient behavior of temperature at central part in hot spot Hot Spot Suppression by Nanofilm Back Coating * Low Power Multi Core Architecture with 3D LSI Stacking Z Direction Connection of TSV Micro Bump Joint Speed: 1~100Gbps Z Direction Connection of Wireless Method Robust Easy Maintenance System High Performance System Z Direction Connection of Optical Method Speed: 10G~1Tbps Speed: 100G~10Tbps Ultra High Performance System IP Chip Optical Inter- connection TSV Micro Bump Joint Inter-connection Inductive/ Capacitive/ Electro-magnetic Inter-connection IP Chip IP Chip PKG Wiring Solder Ball Inter-connection Z Direction Connection of PKG Level Low Cost System IP Chip Speed: 1~100Gbps Signals ：100-10000 Signals ：10-1000 Signals：10-1000 Signals ：10-1000 3D LSI Chip Stacking System Technology COOL System – Ultra Low Power Flexible Extendable Hardware 　NEDO 『Energy Saving Technology RD』　　Collaborative Research with Tops Systems Corp.　 Target：　Ultra Low Power System?Small Volume Production?Short System Development Period 　COOL Chip : Ultra Low Power Heterogeneous Multi Chip 　【3D LSI Stacking Emulation FPGA Board】 　Reduction of Power Consumption with 1/10 Clock Frequency Heterogeneous Multi Core/Multi Chip 　COOL Interconnect : Ultra Low Power Parallel Bus Interface 　 【Interface Test Chip】 　Scalable Connection with Heteroge