Signal Parameters Intel信号参数英特尔.pptVIP

Signal and Timing Parameters ICommon Clock – Class 2 Prerequisite Reading assignment: CH8 to 9.3 Agenda Voltage and Time Budgets Computer Signaling Elements and Circuits Flight time Synchronous Bus Operation Clock Skew and Jitter Setup and Hold Manufacturing Considerations Advanced Topics Voltage and time SI boils down to meeting voltage and time specifications True for most I/O computer interfaces Violating a time or voltage specification i.e. exceeding a limit, may cause a circuit to fail Notice the use of the word “may” rather than “will” Most limits are at least 3 sigma limits. The actual sigma limits are usually a company secret. Margin is the difference between a specification and the respective measured signal parameter. Margin is considered a quality factor for a design. SI Budgets An SI budget is a technique used to report timing and voltage margin in terms of voltage and timing components (“buckets”) for all configurations and conditions of a particular bus design. The budget is often represented in a spread sheet. What Failing SI Means: Negative margin Simple I/O Architecture Pre- ’00 the most common computer I/O interface was synchronous memory transfer Intel Xeon 100 MHz bus was just about the last in this class Clock distribution is a challenge – more on this later Synchronous Memory Elements - Operation Operation A data signal (in) that is present at the input to the flip-flop is “latched” into the flip-flop by the rising edge of the input clock signal (clk). On the next rising edge of clk, the data signal is released to the output of the flip-flop (out). This means data is clocked out of device a on one clock edge and received at device b on the next clock edge. This is also called common clocking. Synchronous Memory Elements - Timing Timing Valid data must be present for a minimum amount of time prior to the input clock edge to guarantee successful capture of the data. This is known as setup time, Tsetup. Data must remain valid for a minimum