may20-23,2014doubletreehotelsanjose,ca.docVIP

May 20-23, 2014 ??Doubletree Hotel ??San Jose, CA /conference/iitc Editor Contacts: Dr. Vincent McGahay Program Co-Chair, 2014 IITC/AMC mcgahay@ Dr. Deepak Chandra Sekar General Co-Chair, 2014 IITC/AMC dsekar@ Dr. Tokei Zsolt General Co-Chair, 2014 IITC/AMC zsolt.tokei@imec.be For Immediate Release Tip Sheet for the 2014 IEEE Joint Conference of the International Interconnect Technology Conference (IITC) and the Advanced Metallization Conference (AMC) The 17th annual?IITC will be held May 21 – 23, 2014 in conjunction with the 31st AMC at the Doubletree Hotel in San Jose, California. It will be preceded by a day-long workshop on “Manufacturing of Interconnect Technologies: Where are we now and where do we go from here?” on Tuesday, May 20.?This tip sheet will provide an advance look at the conference and workshop programs. Further details are available at the conference website: /conference/iitc Please contact us for interviews with conference organizers, for images or for further information. NOTE: See pages 5-7 for: Why interconnect technology is critical to electronics Definitions of technical terms The 2014 IITC/AMC will feature a keynote speech from Dr. Randhir Thakur, Executive Vice President and General Manager of the Silicon Systems Group of Applied Materials. Following this, there will be multiple sessions on 2D and 3D interconnect materials, processes, reliability and systems. Some of the highlights of the technical sessions are: Near-Zero Keep-Out Zone for Through Silicon Via Technology Through Silicon Vias (TSVs), an important component of 3D chip stacking technology, typically have a “keep-out zone” around them, where transistors are not placed. This is due to co-efficient of thermal expansion mismatch between the copper TSVs and silicon, which introduces tensile stresses in the silicon and changes transistor performance. These keep-out zones are typically 7?m, which adds constraints for design and leads to die size penalties.