ComplexProgrammableLogicDevices-ClarksonUniversity.pptVIP

Complex Programmable Logic Devices EE 365 PLDs A General CPLD structure Who makes the CPLDs? The Xilinx 9500-series CPLD Xinlinx CPLDs Architecture of Xilinx 9500-family CPLD Architecture of Xilinx FB XC4000E I/O Block * 16V8 (20 Pins) can have 16 inputs (max) and/or 8 outputs (marcrocells) has 32 inputs to each of the AND gates (product terms) 22V10 (24 pins) can have 22 inputs and/or 10 outputs (max) has 44 inputs to each of the AND gates How about a “128V64” for larger applications? It will be slower and will more wasted silicon space Solution? Use CPLDs GAL16V8(review seq_1.ppt) Each output is programmable as combinational or registered Also has programmable output polarity And Plane The OR gates XOR gates to make inverting or non-inverting buffer A collection of PLDs on a single chip with Programmble interconnects Manufacturer CPLD Products URL Altera MAX 5000, 7000 9000 Altmel ATF ATV Cypress FLASH370, Ultra37000 Lattice ispLSI 1000 to 8000 Philips XPLA Vantis MACH 1 to 5 Xilinx XC9500 Let’s takes a look at this The internal PLDs are called Configurable Functional Blocks (FBs or CFBs) Each FB has 36 inputs and 18 Macrocells (effectively a “36V18”) Each CLPD is packaged in a plastic-leaded chip carrier (PLCC) The number of I/O pins are much less than the total number of Macrocells in family of devices Global set/reset Global 3 state control Global Clock 36 Signal pins 18 outputs 18 Output enable signals Most CLPDs have fewer AND terms per macrocell XC9500 has 5 whereas 16V8 has 8 an