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Modulation of the Schottky Barrier Height for CMOS advanced contacts.pdf

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Modulation of the Schottky Barrier Height for CMOS advanced contacts.pdf

Microelectronic Engineering 156 (2016) 82–85 Contents lists available at ScienceDirect Microelectronic Engineering journal homepage: /locate/mee Modulation of the Schottky Barrier Height for CMOS advanced contacts Mariela A. Menghini a,?, Pia Homm a, Chen-Yi Su a, Jorge A. Kittl b, Ryuji Tomita c, Ganesh Hegde b, Joon-Gon Lee c, Sangjin Hyun c, Chris Bowen b, Mark.S. Rodder b, Valeri Afanasev a, Jean-Pierre Locquet a a Dept. of Physics and Astronomy, KU Leuven, Leuven, Belgium b Advanced Logic Lab, Samsung Semiconductor Inc., Austin, TX, USA c Semiconductor Research and Development, Samsung, Dongtan, Republic of Korea article info Article history: Received 15 June 2015 Received in revised form 7 January 2016 Accepted 8 January 2016 Available online 11 January 2016 Keywords: Schottky Barrier Mosfet SiGe and Ge channel Contact resistance Capacitance measurements abstract Contact schemes for scaled Si, SiGe and Ge channel MOSFET devices are discussed, consistent with an approach based on SiGe alloys with low Schottky Barrier Height (SBH) for pMOS and Si contacts for nMOS, making reduction of the SBH to nSi critical. Contacts to n + Ge with contact resistivity (ρc) values of ~1.5 × 10?8 Ω cm2 are achieved using n + Si passivation. Further, methods for SBH reduction to nSi, and their underlying mechanisms, are studied. Accurate cryogenic CV measurements were used to extract SBH. We show that chalcogenide segregation can be effective in lowering the SBH by a dipole effect, while MIS contacts have a partial un-pinning effect leading to SBH = 0.00 ± 0.01 eV. ? 2016 Elsevier B.V. All rights reserved. 1. Introduction As MOS device dimensions are scaled towards the 7 nm node and beyond, the impact of parasitics such as contact resistance on device performance is becoming dominant. Speci?cally, the metal–semiconductor interface resistance is becoming a large portion of the total device on resistance. Thus, methods to achieve very low metal–semiconductor interface speci?c contac