●TwintubCMOSprocess.docVIP

● Twin-tub CMOS process Provide separate optimization of the n-type and p-type transistors Make it possible to optimize Vt, Body effect, and the Gain of n, p devices, independently. Steps: Starting material: an n+ or p+ substrate with lightly doped - epitaxial or epi layer - to protect latch up Epitaxy Grow high-purity silicon layers of controlled thickness With accurately determined dopant concentrations Electrical properties are determined by the dopant and its concentration in Si C. Process sequence Tub formation Thin-Oxide construction Source drain implantations Contact cut definition Metallization Balanced performance of n and p devices can be constructed. (Substrate contacts are included in Fig.3.10) 3.3 CMOS Process Enhancement (Interconnection) 3.3.1 Metal Interconnect * CMOS circuit = CMOS logic process + Signal/Power/Clock-routing layers Second-layer of metal (VIA1=M1 to M2) Note: M1 must be involved in any contact to underlying areas (polysilicon, diffusion) Process steps for two-metal process (Omitted) 3.3.1.2 Poly Interconnect Polysilicon layer is commonly used as interconnection of signals. Reduce resistance of polysilicon → to make long-distance interconnection Combine polysilicon with a refractory metal (Silicon + Tantalum) 3.3.1.3 Local Interconnection Local Interconnection allow a “direct” connection between ploysilicon and diffusion , alleviating the need for area-intensive contacts and metal Example: Use of Local Interconnect in SRAM (save 25%) 3.3.2 Circuit elements Resistor Polysilicon (undoped) – in static memory cell Resistive metal (Nichrome) to produce high-value, high-quality resistors – in mixed-mode CMOS circuits Capacitors Polysilicon capacitor Memory capacitor (3-dimensional to increase cap/area) Example: Trench capacitor (Fig3.18 (a)) Fin-type capacitor (Fig3.18 (b)) 3.4 Layout Design Rules Function: obtain a circuit with optimum yield in an area as well as possible Performance ←→ yield * Conservative des