利用LP尾M宏功能块调用管理器生成的Verilog文件.docVIP

利用LPM宏功能块调用管理器生成的Verilog文件CNT4B.v，内容如下: // megafunction wizard: %LPM_COUNTER% // GENERATION: STANDARD // VERSION: WM1.0 // MODULE: LPM_COUNTER // ============================================================ // File Name: CNT4B.v // Megafunction Name(s): // LPM_COUNTER // // Simulation Library Files(s): // lpm // ============================================================ // ************************************************************ // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! // // 11.0 Build 157 04/27/2011 SJ Full Version // ************************************************************ //Copyright (C) 1991-2011 Altera Corporation //Your use of Altera Corporations design tools, logic functions //and other software and tools, and its AMPP partner logic //functions, and any output files from any of the foregoing //(including device programming or simulation files), and any //associated documentation or information are expressly subject //to the terms and conditions of the Altera Program License //Subscription Agreement, Altera MegaCore Function License //Agreement, or other applicable license agreement, including, //without limitation, that your use is for the sole purpose of //programming logic devices manufactured by Altera and sold by //Altera or its authorized distributors. Please refer to the //applicable agreement for further details. // synopsys translate_off `timescale 1 ps / 1 ps // synopsys translate_on module CNT4B ( aclr, clk_en, clock, data, sload, updown, cout, q); input aclr; input clk_en; input clock; input [3:0] data; input sload; input updown; output cout; output [3:0] q; wire sub_wire0; wire [3:0] sub_wire1; wire cout = sub_wire0; wire [3:0] q = sub_wire1[3:0]; lpm_counter LPM_COUNTER_component ( .aclr (aclr), .clk_en (clk_en), .clock (clock), .data (data), .sload (sload), .updown (updown), .cout (sub_wire0), .q