怎样提高程序的性能.pptVIP

Secrets of Performance如何提高程序的性能 Bin Lin Development Manager Microsoft Research, China 提高性能的方法 Faster hardware - $$$ = 速度 Use the right language, compiler optimizations Design scalable application Architectural design: cache - RAM - disk Choose right data structures and algorithms Tune code Avoid slow OS APIs Tune, measure, tune, measure, tune, measure… 提高性能的方法 Faster hardware - $$$ = 速度 Use the right language, compiler optimizations Design scalable application Architectural design: cache - RAM - disk Choose right data structures and algorithms Tune code Avoid slow OS APIs Tune, measure, tune, measure, tune, measure… Design: A Case Study Design a scalable SMTP server Scalable is the key 2-CPU, 4-CPU, 8-CPU machines Handle as many request as possible, with relatively fast response time. Design: A Case Study A simple SMTP server // Read SMTP commands/data from sockets If (ReadFile( … )) { // various housekeeping removed… } // Parse SMTP recipients and other headers If (!ParseSMTPHeaders(…)) { // handle errors… } // Parse bodies If (!ParseSMTPBodies(…)) { // handle errors… } Design: A Case Study (cont.) // Local delivery or routing If (LocalDelivery( … )) { Deliver( … ); } else { Route( … ); } // Send SMTP response through Socket If (WriteFile(…)) { // various housekeeping skips… } Traditional Thread Architecture 1 thread to receive and dispatch SMTP request 64 worker threads doing: Parse SMTP headers Parse SMTP bodies Local delivery Routing All in the same thread sequentially… The Evolution of Hardware Bridge the Gap - Caches CPU L1 cache 8K instruction cache, plus 8K data cache Closely coupled 0.333 clock/instruction – practical 1 CPI CPU L2 cache 512K static RAM Coupled with full clock-speed, 64-bit, cache bus Latency: 4-1-1-1 – 7 clocks/instruction I/O caches (RAM based file caches) The Price of Failure Let’s look at the costs: Assume 1 second to zero a register L1 cache hit - 1 second (1x) L2 cache hit - 4 seconds (plus 3 seconds extra