EDA例题.doc

3-3：图3-31所示的是双2选1多路选择器构成的muxk,对于其中MUX21A，当S=’0’和‘1’时，分别有y=a和y=b。试在一个结构体中用两个进程来表达此电路。每个进程用if/case语句描述一个2选一多路选择器mux21a。 图3-31 双2选1多路选择器 Library ieee; Use ieee.std_logic_1164.all; Entity muxk1 Is port(a1,a2,a3,s0,s1: In std_logic; outy: Out std_logic); End muxk1; Architecture abmux Of muxk1 Is Signal tmp: std_logic; Begin p1: process (a2,a3,s0) Begin Case s0 is When ‘0’ = tmp = a2; When ‘1’ = tmp = a3; When others = Null; End Case; End process; p2: Process (a1,tmp,s1) Begin Case s1 is When ‘0’ = outy = a1; When ‘1’ = outy = tmp; When others = Null; End Case; End Process; End abmux; Library ieee; Use ieee.std_logic_1164.all; Entity muxk is Port(a1,a2,a3,s0,s1: In Std_logic; outy: Out Std_logic); End muxk; Architecture abmux Of muxk is Signal tmp: Std_logic; Begin p1: Process (a2,a3,s0) Begin If s0=1 Then tmp = a2; Else tmp = a3; End If; End Process; p2: Process (a1,tmp,s1) Begin If s1=1 Then outy = a1; Else outy= tmp; End if; End Process; End abmux; 3-4 给出一位全减器的VHDL描述，要求： 首先设计1位半减器，然后用例化语句将他们连接起来，图3-32中h_suber是半减器，diff是输出差，s_out是借位输出，sub_in是借位输入。 以1位全减器为基本硬件，构成串行借位的8位减法器，要求用例化语句来完成此项设计（x-y-subin=diffr）。 半减器程序 LIBRARY IEEE ; USE IEEE.STD_LOGIC_1164.ALL ; ENTITY h_suber IS PORT (x,y : IN STD_LOGIC ; diff,s_out: OUT STD_LOGIC); END ENTITY h_ suber; ARCHITECTURE h OF h_suber IS SIGNAL ab：STD_LOGIC_VECTOR（1 DOWNTO 0）； BEGIN ab = x y； PROCESS（ab） BEGIN CASE ab IS WHEN “11” = diff = ‘0’； s_out = ‘0’； WHEN “10” = diff = ‘1’； s_out = ‘0’； WHEN “01” = diff = ‘1’； s_out = ‘1’； WHEN “00” = diff = ‘0’； s_out = ‘0’；