TEC-2000控制器相关VHDL代码.docVIP

TEC-2000系统控制器部件相关程序的VHDL语言 程序清单 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity controller is; port(clock:in std_logic; 　　reset :in std_logic; 　　ir :out std_logic_vector(15 downto 0); 　　dr :out std_logic_vector(3 downto 0); 　　sr :out std_logic_vector(3 downto 0); 　　flag_c :in std_logic; 　　flag_z :in std_logic; 　　ib :inout std_logic_vector(15 downto 0); 　　a_sel :out std_logic; 　　b_sel :out std_logic_vector(1 downto 0); 　　reg_src :out std_logic_vector(1 downto 0); 　　reg_wt :out std_logic; 　　r_sel :out std_logic_vector(1 downto 0); 　　s_sel :out std_logic_vector(1 downto 0); 　　alu_func :out std_logic_vector(2 downto 0); 　　flag_func :out std_logic_vector(2 downto 0); 　　y_sel :out std_logic; 　　ar_wt :out std_logic; 　　y_ib :out std_logic; 　　gate_en :out std_logic; 　　gate_dir :out std_logic; 　　mio :out std_logic; 　　req :out std_logic; 　　we :out std_logic; 　　time_cyc :out std_logic_vector(2 downto 0); 　　pc_out :out std_logic_vector(15 downto 0); 　　addr_sel :out std_logic_vector(1 downto 0); 　　end controoler; 　　architecture behavioral of controller is signal pc_src :std_logic_vector(1 downto 0); signal timing :std_logic_vector(2 downto 0); signal adder_output :std_logic_vector(15 downto 0); signal pc :std_logic_vector(15 downto 0); signal npc :std_logic_vector(15 downto 0); signal ir_inter :std_logic_vector(15 downto 0); signal offset :std_logic_vector(15 downto 0); signal pc_input :std_logic_vector(15 downto 0); signal icode :std_logic_vector(15 downto 0); signal add_src :std_logic; signal pc_wt :std_logic; signal ir_wt :std_logic; signal npc_ib :std_logic; signal npc_wt :std_logic; begin icode =ir_inter(15 downto 8); dr =ir_inter(7 downto 4); sr =ir_inter(3 downto 0); time_keeper:process(clock,reset) begin if(reset=1) then timing=100; elseif rising_edge(clock) then