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CDCLVD1208RHDT;CDCLVD1208RHDR;中文规格书,Datasheet资料
FPGA
CDCLVD1208
LVDS Buffer
IN_SEL
PHY2
PHY2
PHY2
PHY2
PHY2
PHY2
PHY 7
125 MHz
125 MHz
Oscillator
CDCLVD1208
SCAS899 –AUGUST 2010
2:8 Low Additive Jitter LVDS Buffer
Check for Samples: CDCLVD1208
1FEATURES
DESCRIPTION? 2:8 Differential Buffer
? Low Additive Jitter: 300 fs RMS in The CDCLVD1208 clock buffer distributes one of two
selectable clock inputs (IN0, IN1) to 8 pairs of10 kHz to 20 MHz
differential LVDS clock outputs (OUT0, OUT7)
? Low Output Skew of 45 ps (Max)
with minimum skew for clock distribution. The
? Universal Inputs Accept LVDS, LVPECL,
CDCLVD1208 can accept two clock sources into an
LVCMOS input multiplexer. The inputs can either be LVDS,
LVPECL, or LVCMOS.? Selectable Clock Inputs through Control Pin
? 8 LVDS Outputs, ANSI EIA/TIA-644A Standard The CDCLVD1208 is specifically designed for driving
Compatible 50 Ω transmission lines. If the input is in single ended
mode, the appropriate bias voltage (V
AC_REF
) should? Clock Frequency up to 800 MHz
be applied to the unused negative input pin.
? 2.375–2.625V Device Power Supply
The IN_SEL pin selects the input which is routed to
? LVDS Reference Voltage, VAC_REF, Available for
the outputs. If this pin is left open it disables the
Capacitive Coupled Inputs
outputs (static). The part supports a fail safe function.
? Industrial Temperature Range –40°C to 85°C
It incorporates an input hysteresis, which prevents
random oscillation of the outputs in absence of an? Packaged in 5mm × 5mm 28-Pin QFN (RHD)
input signal
? ESD Protection Exceeds 3 kV HBM, 1 kV CDM
The device operates in 2.5 V supply environment and
APPLICATIONS is characterized from –40°C to 85°C (ambient
temperature). The CDCLVD1208 is packaged in? Telecommunications/Networking
small 28-pin, 5-mm × 5-mm QFN package.
? Medical Imaging
? Test and Measurement Equipment
? Wireless Communications
? General Purpose Clocking
Figure 1. Application Example
1
Please be aware that an important notice concerning availability, standard warranty, and use in
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