ICE Overview.pdf

Informed Caching Environment Alvin R. Lebeck Computer Science Department Duke University /ari/ice alvy@ Informed Caching Environment 2Alvin R. Lebeck P $ Memory Very fast, 1ns clock, Multiple Instructions per cycle SRAM, Fast, Expensive, Small DRAM, Slow, Big, Cheap = Cost Effective Memory System (Price/Performance) Cache Memory Review Informed Caching Environment 3Alvin R. Lebeck ? Hardware Managed ? Use naive history of past references to manage content ? No information from Program! P $ Memory Current Caches Are Naive Informed Caching Environment 4Alvin R. Lebeck ? Augment conventional cache with set of sophisticated mechanisms ? Exploit information from program to improve cache management, thus overall performance P $ Memory Informed Caching Environment Informed Caching Environment 5Alvin R. Lebeck Outline ? Motivation ? ICE Overview ? Annotated Memory References ? Exploiting Information on Temporal and Spatial Locality ? Latency Tolerance in Dynamically Scheduled Processors ? Conclusion Informed Caching Environment 6Alvin R. Lebeck Three Aspects of ICE ? How to obtain information? Profiling, user directives, compiler, HW gadgets ? How to convey information? Instructions, TLB, HW gadgets ? How to exploit the information? New mechanisms, HW gadgets Informed Caching Environment 7Alvin R. Lebeck What Information? ? Locality – Temporal: reuse same data items – Spatial: use nearby data – Use for cache replacment or fetch size ? Latency tolerance in dynamically scheduled processors (e.g., Alpha 21264) – can tolerate some long latency loads ? Pointer Chasing ? Hints, not required for correct execution Informed Caching Environment 8Alvin R. Lebeck What Mechanisms? ? Annotated memory references to convey information – Can annotate either instruction (PC) or data (effective address) – New Instruction, Compiler or programmer inserted – Hardware Gadgets ? Locality – Retain / Release Operations – Variable block size ? Latency tolerance – Keep tolerant data in slower