L2 Silicon Track TriggerD0 Trigger Workshop.ppt

L2 Silicon Track TriggerD0 Trigger Workshop22 April 2002 Ulrich Heintz Boston University People and Institutions Boston University Ulrich Heintz, Meenakshi Narain Evgeny Popkov, Lars Sonnenschein, Jodi Wittlin Kevin Black, Sarosh Fatakia, Lorenzo Feligioni, Alex Zabi Eric Hazen, Bill Earle, Shouxiang Wu Columbia University Hal Evans Georg Steinbrück Tulika Bose An Qi Florida State University Horst Wahl, Todd Adams, Sue Blessing, Stephen Linn, Harrison Prosper Bill Lee, Sylvia Tentinto-Repond Reginald Perry, Arvindh Lalam, Shweta Lolage SUNY Stony Brook John Hobbs Wendy Taylor Huishi Dong Chuck Pancake, Bonnie Smart, Jane Wu STT Functionality Include SMT data in track trigger Only available at level 2 Use level 1 tracks as seeds for roads Search for SMT hits in roads Perform fit to SMT + CFT hits Conceptual Design L1CTT?tracks in CFT Define road in SMT Select SMT hits in roads Fit trajectory to L1CTT+SMT hits. Measure pT, impact parameter, azimuth Send results to L2 Pass L1CTT information to L2 Send SMT clusters to L3 Motherboard 9Ux400mm VME board SCL mezzanine card (FRC) Up to 6 link boards Logic card Buffer controller Dedicated lines SCL?logic card VTM?logic card 3 PCI busses (32bit/33MHz) Link boards?logic card Buffer controller?logic card Universe II bridge PCI bus to VME bus Motherboard Link Transmitter/Receiver Boards PCMIP standard 3 LVDS serial links 24 bits @ 66 MHz 16 data bits Single bit error correction Multibit error detection 1012 bits w/o error 256k buffer design complete Fiber Road Card SCL Receive 128 bits every 132 ns Fan out L1_QUAL, L1_TURN, L1_BX L1CTT data Receive 1.5 Gbit/s glink ? VTM Fan out manage L3 buffers control allocation/deallocation of L3 buffers send readout requests to VBD send monitoring requests to CPU arbitrate VME bus FRC Buffer controller FRC Silicon Trigger Card Strip reader Cluster finder Hit filter SMT L1CTT Road LUT SCL L3 L3 TFC via serial link from FRC via serial link control logic 31 30 29 28 27 26 25 24 23 22