Efficient gate delay modeling for large interconnect loads.pdf

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2017-04-11 发布于江苏
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Efficient gate delay modeling for large interconnect loads.pdf

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Efficient gate delay modeling for large interconnect loads

Ecient Gate Delay Modeling for Large Interconnect Loads Andrew B. Kahng and Sudhakar MudduUCLA Computer Science Department, Los Angeles, CA 90095-1596 USAabk@cs.ucla.edu, sudhakar@cs.ucla.eduAbstractWith fast switching speeds and large interconnect trees (MCMs), the resistance and inductance ofinterconnect has a dominant impact on logic gate delay. In this paper, we propose a new modelfor distributed RC and RLC interconnects to estimate the driving point admittance at the outputof a CMOS gate. Using this model we are able to compute the gate delay eciently, within 25%of SPICE-computed delays. Our parameters depend only on total interconnect tree resistanceand capacitance at the output of the gate. Previous \eective load capacitance methods [7, 9],applicable only for distributed RC interconnects, are based on model parameters obtained via arecursive admittance moment computation. Our model should be useful for iterative optimizationof performance-driven routing or for estimation of gate delay and rise times in high-level synthesis.Keywords: gate delay, reduced-order models, driving point admittance, eective capacitance,interconnect modeling1 IntroductionAs the feature size of integrated circuits decreases, gate delays decrease and interconnect delaysincrease. The overall logic-stage delay consists of a gate delay component plus an interconnectdelay component. Previously, the gate delay component could be estimated by modeling theentire interconnect tree at the gate output as a simple lumped capacitance. Now, with increasedinterconnect resistance and larger interconnect trees, the lumped capacitance approximation re-sults in pessimistic delay and rise time calculations. Accurate estimation of gate delay and risetime closely depends on the model for the driving point admittance of a load interconnect treeat the output of a gate.Furthermore, with interconnect delays dominating overall path delays for current integratedcircuits, algorithms for synthesis and layo