FECCoreAreaComparisonandModel.PDFVIP

FEC Core Area Comparison and Model Martin Langhammer Altera Corporation P802.3bs 400Gb/s Ethernet Task Force 1 Overview ? This presentation will show the relative areas of FEC cores used in recent 802.3bs meetings – Focusing on Reed Solomon and BCH ? A modelling method will be introduced to allow a quick area calculation for similar types of cores – Only primary school math required ? Quick tutorial on Reed Solomon and BCH core architectures – Block diagrams 2 Caveats ? This presentation does not consider the merits of any FEC – Gain – Latency – Suitability for a channel or application ? This presentation introduces a model to allow a relative area comparison of different Reed Solomon and BCH FECs – Based on codeword parameters (n,k,t) ? Throughput important consideration (parallelism) – Monolithic or individual pipes ? Model is not normalized for gain and latency ? FEC only – does not consider PCS area, complexity etc. – FEC alone may be a significant consideration 3 Modelling Complications - FPGA vs. ASIC ? Memory vs. Logic – FPGA has some amount of memory blocks interspersed with logic ? Subfield Inversion (polynomial calculation, Forney) ? Delay lines ? Different types of logic – FPGA typically basic building block 6 input LUT (look up table) ? (Altera: ALM, Xilinx: 6LUT) – FPGA Registers free with logic 6 LUT ? Performance – ASIC typically 650MHz, 2 clocks per polynomial iteration1 – FPGA typically 325MHz, 2 clocks per iteration ? Latency vs. Latency – 100ns ASIC vs. 250-350ns FPGA ? Summary: exact comparison cannot be made, too many variables – First model will ignore effects of regis