常用電路VHDL描述.pptVIP

5.4 常用电路VHDL描述 ;ARCHITECTURE bhv OF DFFl 1S BEGIN PROCESS(CLK) BEGIN IF CLK’EVENT AND CLK=‘1’THEN Q=D； END IF； END PROCESS； END bhv；;IF语句的完整格式为：IF- THEN- ELSE- END IF。通常，完整的条件语句只能构成组合逻辑电路。 VHDL利用不完整的条件语句的描述引进寄存器元件，从而构成时序电路的方式是VHDL描述时序电路最重要的途径。 注意在利用条件语句进行纯组合电路设计时，要充分考虑电路中所有可能出现的问题，当没有列全所有的条件及其对应的处理方法，会导致不完整的条件语句的描述，从而产生设计者不希望的时序电路。 ;【例5-17】与门的错误描述：如果输入A、B同时为1，输出C就为1。 ;ARCHITECTURE behave OF and2 IS BEGIN PROCESS(a , b) BEGIN IF (a＝‘1’AND b＝‘1’) THEN c＜＝‘1’; END IF; END PROCESS; END behave;;【例5-18】1位数据比较器的错误描述。;ARCHITECTURE One OF COMP_BAD IS BEGIH PROCESS (al，b1) BEGIN IF a1bl THRN ql=’1’； ELSIF albl THEN ql=’0’; END IF； END PROCESS ； END One；;5.4.2 加法器 ;ARCHITECTURE behave OF adder8 IS SIGNAL halfadd, fulladd : std_logic_vector (8 DOWNTO 0); BEGIN halfadd＜＝data 1+ data 2; fulladd＜＝halfadd WHEN ci =‘0 ’ ELSE halfadd+1; result＜＝fulladd (7 DOWNTO 0); co＜＝fulladd(8)； END behave; ;5.4.3 译码器 ;ARCHITECTURE BODY OF HEXLED IS BEGIN PROCESS(HEX) BEGIN CASE HEX IS WHEN 0000 = led= 0111111; WHEN 0001 = led= 0000110; WHEN 0010 = led= 1011011; WHEN 0011 = led= 1001111; WHEN 0100 = led= 1100110; WHEN 0101 = led= 1101101; WHEN 0110 = led= 1111101; WHEN 0111 = led= 0000111;;5.4.4 编码器;ARCHITECTURE behave OF encoder IS BEGIN q= “111” WHEN d(7) = ‘1’ ELSE “110” WHEN d(6) = ‘1’ ELSE “101” WHEN d(5) = ‘1’ ELSE “100” WHEN d(4) = ‘1’ ELSE “011” WHEN d(3) = ‘1’ ELSE “010” WHEN d(2) = ‘1’ ELSE “001” WHEN d(1) = ‘1’ ELSE “000” WHEN d(0) = ‘1’ ELSE “000” ; END behave; ;【例5-23】8-3优先编码器。用IF语句。实体略。;5.4.5 三态门输出电路;ARCHITECTURE behave OF triout IS BEGIN data_out＜＝data_in WHEN oe_en = ‘1’ ELSE (OTHERS = ‘Z’）； END behave;;5.4.7移位寄存器;同步清零（RES=1），同步置数（MOD