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Interconnect delay minimization through interlayer via placement
Interconnect Delay Minimization through Interlayer Via
Placement in 3-D ICs
Vasilis F. Pavlidis, Eby G. Friedman
Department of Electrical and Computer Engineering
University of Rochester
Rochester, New York 14627, USA
[pavlidis, friedman] @ ece.rochester.edu
ABSTRACT
The dependence of the propagation delay of the interlayer 3-D
interconnects on the vertical through via location and length is
investigated. For a variable vertical through via location, with fixed
vertical length, the optimum vertical through via location that
minimizes the propagation delay of an interconnect line connecting
two circuits on different planes is determined. The optimum vertical
through via location and length or, equivalently, the number of
physical planes traversed by the vertical through via, are determined
for varying the placement of the connected circuits. Design
expressions for the optimal via locations and lengths have been
developed to support placement and routing algorithms for 3-D ICs.
Categories and Subject Descriptors
B.7.2 [Design Aids]
General Terms: Performance, Design.
Keywords: 3-D ICs, Elmore delay, RC Interconnects.
1. INTRODUCTION
Technology scaling has enabled an increase in integration density
and a considerable decrease in the intrinsic gate delay, through
smaller and faster devices. Higher integration densities require both
a greater number of interconnects and longer interconnects.
Therefore, as the device delay is reduced, the performance of the
integrated circuits is now dominated by the interconnect delay. In
addition, other interconnect related issues, such as power
consumption and signal integrity, have become more pronounced
with technology scaling. To manage these issues, a variety of
techniques have been developed, such as tapered buffers, repeater
insertion, wire sizing, and shielding, to name a few. Nonetheless,
these techniques increase silicon area and power consumption. As a
result, innovative design processes are
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