Interconnect delay minimization through interlayer via placement.pdfVIP

Interconnect Delay Minimization through Interlayer Via Placement in 3-D ICs Vasilis F. Pavlidis, Eby G. Friedman Department of Electrical and Computer Engineering University of Rochester Rochester, New York 14627, USA [pavlidis, friedman] @ ece.rochester.edu ABSTRACT The dependence of the propagation delay of the interlayer 3-D interconnects on the vertical through via location and length is investigated. For a variable vertical through via location, with fixed vertical length, the optimum vertical through via location that minimizes the propagation delay of an interconnect line conn