计算机系统结构复习题汇编.docxVIP

Question 4A single-issue processor uses tomasulo’s algorithm in its floating-point unit, which has one adder and one multiplier,each with its own set of reservation station,there is only one CDB ,and broadcast on this CDB takes an entire cycle.the processor is executing the following sequence of instruction and, for each instruction ,we show the cycle in which the instruction is fetched,decoded,issued,begins to execute,and writes result.单发射处理器在其浮点单元中使用托马斯算法，其具有一个加法器和一个乘法器，每个具有其自己的一组保留站，只有一个CDB，并且在该CDB上广播需要整个周期。处理器正在执行以下指令序列，并且对于每个指令，我们示出指令被取出，解码，发出，开始执行和写入结果的周期。instructionfetchdecodeissueexecuteWrite resultI1MUL R1,R2,R212348I2ADD R1,R1,R2234910I3MUL R2,R2,R3345813I4ADD R3,R1,5MUL R1,R1,6ADD R2,R3,R46711????I7ADD R1,R5,?hat is the latency of the multiplier?4Is the multiplier pipelined?NHow many reservation station are there for the adder?2In which cycle does I6 begin to execute? 13Which register does ?? Represent in I7R1If the priory for using CDB depends on the type of instruction,between ADD and MUL the priority for using the CDB goes to ___? ADDQuestion 8（书本92页）.Loop: LD R1,0(R2) ;load R1 from address 0+R2DADDI R1,R1,#1 ;R1=R1+1SD R1,0,(R2) ;store R1 at address 0+R2DADDI R2,R2,#4 ;R2=R2+4DSUB R4,R3,R2 ;R4=R3-R2BNEZ R4,Loop;branch to Loop if R4!=0Assume that the initial value of R3 is R2 + 396.答案：（1）依题意可得，指令序列执行的流水线时空图如下：1234567891011121314151617181920211IFIDEXMEWB2IFIDEXMEWB3IFIDEXMEWB4IFIDEXMEWB5IFIDEXMEWB6IFIDEXMEWB1IFIFIDEXME时钟周期为：17*98+18 = 1684 （2）依题意可得，指令序列执行的流水线时空图如下：1234567891011121314151IFIDEXMEWB2IFIDSEXMEWB3IFSIDEXMEWB4IFIDEXMEWB5IFIDEXMEWB6IFIDEXMEWB7IFMissMissIFIDEXMEWB时钟周期为：10*98+11 = 991 （3） 依题意可得，指令序列执行的流水线时空图如下：12345678910111IFIDEXMEWB2IFIDEXMEWB3IFIDEXMEWB4IFIDEXMEWB5IFIDEXMEWB6IFIDEXMEWB1IFIDEXMEWB时钟周期为：6*98+10 = 598Question 99a) What is the effective access time of a cache memory system in which thereis a 2-way set associative cache, having the following parameters:Parameter: Value:number of sets 1024 setsline siz