vhdl基本语素、语法、语句[杨].pptVIP

数字电路与逻辑设计;一、基于VHDL的组合逻辑分析;library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity sswr is port(d:in std_logic_vector(3 downto 0); y:out std_logic); end sswr;; architecture behave of sswr is begin y = 0 when d=0 and d5 else 1 when d=5 and d10 else Z; end behave;;library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity FBI is port(a,b,ci:in std_logic; y,cout:out std_logic); end FBI ;;architecture bh2 of FBI is begin y = a xor b xor ci;