TurboPMACCPUandMemory.PDFVIP

Turbo PMAC Application Notes Turbo PMAC CPU and Memory Configurations Turbo PMAC controllers can be provided with several different CPU and memory configurations. The user specifies the desired configuration by ordering one of the Opt 5xx CPU options. The x immediately following the 5 is a letter specifying the processor type, each with different speed and internal memory capacity. The second x is a number specifying the amount of memory external to the processor. Processor Types Turbo PMAC controllers use digital signal processors (DSPs) from Freescale (formerly Motorola) of the DSP563xx family. Harvard Architecture Memory The Freescale (formerly Motorola) DSP563xx CPUs used in Turbo PMAC controllers utilize a Harvard architecture, with separate memory banks for data and instructions. This architecture is more efficient, but less flexible, than the more common von Neumann architecture used in most general-purpose computers. In a given application, a given bank of physical memory cannot be switched between the two uses. Each CPU/memory configuration of the Turbo PMAC makes a specific division between the two banks of memory, and this division cannot be changed by the user. Instruction (Program) Memory The instruction memory bank contains the actual machine-code instructions executed by the processor. These instructions must have been compiled or assembled from the source code before loading into the Turbo PMAC memory. This bank is called the P (program) memory bank, and is very seldom accessed directly by a user. Each instruction register is a 24-bit word. There are four possible sets of instructions in the P memory bank: 1. Firmware: This code is written and loaded by Delta Tau, and must be present for the Turbo PMAC to operate. 2. Compiled PLCs: The user can load up to 32 compiled PLC programs into Turbo PMAC’s P memory. The download routines of the Executive program and PCOMM library automatical