INTERCONNECTMODELING.pptVIP

INTERCONNECT MODELINGM.Arvind2nd M.E Microelectronics OVERVIEW Introduction to On-Chip interconnects Modeling the parasitics Elmore Delay Model Repeater insertion Min delay condition Power Model Optimizing Power  Introduction to On-chip interconnects  Wires linking the transistors together Three types of interconnects : Local Semi-global and Global interconnect Introduction to On-chip interconnects Can be modeled as R, RC, LC, RLC or RLGC network. Modeling a piece of wire Capacitance Modeling Capacitance cw = 2 * (cg + cf * cc ) cf is the coupling factor Capacitance Modeling (cont) cg has 2 components: cg1, cg2 Simplified Capacitance Model For a circuit designer ILDT, h and ε are fixed. Therefore, Fringing Effects Modeling Wire Resistance Resistance Pros and Cons of Cu Pros Better electro-migration resistance Cons Cu atoms diffuses into SiO2 Cladding layers of TiN, Si3N4 used to prevent this Increases the resistance Elmore Delay Model Delay of a RC network is given by Delay of a long wire Delay grows quadratic Hence need repeaters Repeater Insertion Repeaters are placed to reduce delay Repeater Insertion (cont) Delay grows linear Modeling the repeater Repeater is a large inverter (5-25μm) placed in-between interconnect lines. Cgate, Cp α size of the repeater RT = VDD/2*Iavg, where Iavg = ∫Iddt in the interval Td Modeling the repeater (cont) Delay equations Delay of an interconnect segment is Total delay is Optimal Repeater Size and Spacing The minimum delay condition Power modeling Total power dissipated in the interconnect network is given by Ptotal= Pdy + Psc + Pleak Pdy = ?Ctotal V2ddf Psc = ?Isc per μm Vdd Wtotalftt Pleak = Ileak per μm WtotalVdd Where ? is the switching factor, tt is the time taken for the input to transit from Vthn to Vdd – Vthp Power modeling (cont) Optimizing power Min delay does not imply min power Techniques to Reduce Power Can be reduced by decreasing Supply voltage Size of repeaters