Mismatch-ShapingSuccessive-ApproximationADC.pdfVIP

Mismatch-Shaping Successive-Approximation ADC Matthew Coe and Un-Ku Moon Oregon State University moon@ece.orst.edu Abstract A mismatch-shaping scheme is proposed for a 16-bit successive-approximation ADC based on a simple two capacitor charge-redistribution DAC where the mismatch estimates are accurate to the first order. A digital state machine is used to control the switching sequence of the D/A conversion. A second order delta-sigma loop was found to be effective in system simulations given a 0.1% capacitor mismatch. Spectral analysis of the ADC shows dramatic improvement in total harmonic distortion as well as 87 dB SNDR (signal to noise and distortion ratio) for an oversampling ratio (OSR) of 10. Keywords: Mismatch-shaping, Capacitor mismatch, Data converters, ADC, Successive-approximation, Switched capacitor, Delta-sigma 1. Introduction A successive-approximation ADC employs The performance of analog integrated the binary search algorithm in order to find the digital circuits is generally limited to the matching accuracy code which most closely matches the analog input of their components. A recent approach to value. In order to obtain an N bit digital word the systematically solving this problem is to use digital binary search algorithm must be carried out N times, logic to perform a shuffling of nominally matched requiring N clock cycles. During this time, the input components so that the noise introduced by voltage must not change, which requires the use of component mismatch can be controlled [1][2]. The