《数字电子技术基础第二版》3.10组合逻辑电路的分析和设计.pptVIP

3.10 VHLD描述组合逻辑电路 上页 下页 后退 模拟电子 数字电子技术基础 上页 下页 返回 3.10.1 VHLD描述常用组合逻辑电路 LIBRARY IEEE USE IEEE.std_logic_1164.all ENTITY decoder3_8 IS PORT (A2, A1, A0, STA, STB, STC: IN STD_LOGIC; Y : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); 【例1】 3线-8线译码电路的VHDL程序 END decoder3_8; ARCHITECTURE rt1 OF decoder3_8 IS SIGNAL indate: STD_LOGIC_VECTOR(2 DOWNTO 0) ; BEGIN Indate = A2 A1 A0; PROCESS(indate ,STA , STB, STC) BEGIN IF(STA=‘1’ AND STB=‘0’ AND STC=‘0’) THEN CASE indate IS WHEN “000” =Y=; WHEN “001” =Y=; WHEN “010” =Y=; WHEN “011” =Y=; WHEN “100” =Y=; WHEN “101” =Y=; WHEN “110” =Y=; WHEN “111” =Y=; WHEN OTHERS =Y=; END CASE; ELSE Y=; END IF; END PROCESS; END rt1; 【例2 】 四选一多路选择器的VHDL程序 ENTITY selsig IS PORT ( d0, d1, d2, d3 : IN BIT; address : IN INTEGER RANGE 0 TO 3; y : OUT BIT ); END selsig; ARCHITECTURE maxpld OF selsig IS BEGIN WITH address SELECT y = d0 WHEN 0; d1 WHEN 1; d2 WHEN 2; d3 WHEN 3; END maxpld; 【例 3】 8位二进制加法器 ENTITY add IS PORT(a, b:IN INTEGER RANGE 0 TO 7 ; z :OUT INTEGER RANGE 0 TO 15 ); END add; ARCHITECTURE arithmetic OF add IS BEGIN z = a + b; END arithmetic; 3.10.2 用VHLD描述一般组合逻辑电路 【例4】 记录一个字节中1的个数的VHDL程序 LIBRARY IEEE; USE IEEE.std_logic_1164.all; ENTITY proc; PORT ( d : IN BIT_VECTOR(2 DOWNTO 0); q : OUT INTEGER RANGE 0 TO 3); END proc; ARCHITECTURE maxpld OF proc IS BEGIN PROCESS(d) VARIABLE num_bits :INTEGER; BEGIN num_bits : =0; FOR i IN d ‘ RANGE LOOP IF d(i) = ‘1’ THEN num_bits : = num_bits + 1 END IF; END LOOP; q = num_bits; END PROCESS; END maxpld;