Redundant Logic Insertion and Latency Reduction in Self-Timed Adders 外文参考文献.docVIP

HindawiPublishingCorporation VLSIDesign Volume2012,ArticleID575389,13pages doi:10.1155/2012/575389 ResearchArticle RedundantLogicInsertionandLatencyReductionin Self-TimedAdders andW.B.Toms P.Balasubramanian,1,2D.A.Edwards,3 3 1 2 3 DepartmentofElectronicsandCommunicationEngineering,VelTechDr.RRandDr.SRTechnicalUniversity,Avadi, TamilNadu,Chennai600062,India DepartmentofElectronicsandCommunicationEngineering,S.A.EngineeringCollege,AnnaUniversity,Thiruverkadu, TamilNadu,Chennai600077,India SchoolofComputerScience,TheUniversityofManchester,OxfordRoad,ManchesterM139PL,UK Corres