Towardsasub-2.5V,100-GbsSerialTransceiver-IEEE2007.PDF

IEEE 2007 Custom Intergrated Circuits Conference (CICC) Towards a sub-2.5V, 100-Gb/s Serial Transceiver S.P. Voinigescu, R. Aroca, T.O. Dickson1, S.T. Nicolson, T. Chalvatzis, P. Chevalier*, P. Garcia*, C. Garnier*, and B. Sautreuil* Edward S. Rogers Dept. of ECE, University of Toronto, 10 Kings College Rd., Toronto, ON, M5S 3G4, Canada *) STMicroelectronics, 850 rue Jean Monnet, F-38926, Crolles, France 1) Now with IBM T.J. Watson Research Center, 1101 Kitchawan Road MS 40-141, Yorktown Heights, NY Abstract-This paper describes first a half-rate, 2.5-V, 1.4-W, 87- consumption must be lowered in SiGe BICMOS-based Gb/s transmitter with on-chip PLL fabricated in a production transceivers or a 1.2V CMOS technology capable of 100-Gb/s 130-nm SiGe BiCMOS process. Next, the most critical blocks speeds must be developed. required for the implementation of a full-rate 100-Gb/s serial transceiver are explored. State-of-the art 105-GHz, SiGe HBT static frequency dividers and VCOs operating from 2.5-V supply, RP RP as well as 65-nm CMOS, 1.2-V, 90-GHz static frequency dividers, low-phase noise VCOs, and 100-GHz clock distribution network LP LP amplifiers are fully characterized over power supply and process spread, and over temperature up to 100oC. Inductor and DOUT transformer modeling and scaling beyond 200 GHz in nanoscale CMOS and SiGe BiCMOS technologies, are also described. Q1 Q2