邓仰东基于GPU的高性能嵌入式计算CUDA技术沙龙.pptVIP

The routing table contains information about the topology of the network immediately around it. The construction of routing tables is the primary goal of routing protocols. A Network Intrusion Detection System (NIDS) is an intrusion detection system that tries to detect malicious activity Microarchitectural Enhancements Uniformly one thread for one packet No thread block necessary Directly schedule and issue warps GPU fetches packet IDs from task queue when Either a sufficient number of packets are already collected Or a given interval passes after last fetch CPU-maintained task queue Delayed Commit Queue GPU Core GPU Core GPU Core GPU Core GPU Core GPU Core Results: Throughput Results: Packet Latency Outline Motivation and background Morphing GPU into a network processor High performance radar DSP processor Conclusion High Performance Radar DSP Processor Motivation Feasibility of GPU for DSP processing Designing a massively parallel DSP processor Research Objectives High performance DSP processor For high-performance applications Radar, sonar, cellular baseband, … Performance requirements Throughput ≥ 800GFLOPs Power Efficiency ≥ 100GFLOPS/W Memory bandwidth ≥ 400Gbit/s Scale to multi-chip solutions Current DSP Platforms *GDDR5: Peak Bandwidth 28.2GB/s Processor Frequency # cores Throughput Memory Bandwidth Power Power Efficiency (GFLOPS/W) TI TMS320C6472-700 500MHz 6 33.6GMac/s NA 3.8W 17.7 FreeScale MSC8156 1GHz 6 48GMac/s 1GB/s 10W 9.6 ADI TigerSHARC ADSP-TS201S 600MHz 1 4.8GMac/s 38.4GB/s (on-chip) 2.18W 4.4 PicoChip PC205 260MHz 1GPP+ 248DSPs 31GMac/s NA 5W 12.4 Intel Core i7 980XE 3.3GHz 6 107. 5GFLOPS 31.8GB/s 130W 0.8 Tilera Tile64 866MHz 64 CPUs 221GFLOPS 6.25GB/s 22W 10.0 NVidia Fermi GPU 1GHz 512 scalar cores 1536GFLOPS 230GB/s * 200W 7.7 High Performance Radar DSP Processor Motivation Feasibility of GPU for DSP processing Designing a massively parallel DSP processor HPEC Challenge - Radar Benchmarks Benchmark Description TDFIR Time-domain finite i