【经验分享】Keystone架构DSP原理图设计检查表.pdfVIP

1. Device configuration, a) There are three dedicated configuration pins, CORECLKSEL, and DDRSLRATE1:0. The state of these pins is not latched and must be held at the desired state at all times. b) Boot Modes: When implementing the pull-up or pull-down boot scheme selected, TI recommends a 1k resistor to the correct polarity. 2. Clocking a) All differential clock input buffers are low jitter clock buffers (LJCBs). b) Any unused LJCB inputs should be connected to the appropriate rails to establish a valid logic level. c) Because the common mode biasing is included, the clock source must be AC coupled (except where noted in this document and data sheet).(0.1uF) d) All clock drivers must be in a high impedance state until CVDD (at a minimum) is at a valid level. e) In hardware design guide, “If the both of the SGMII interfaces are not used, the SGMII regulator power pin (VDDR3_SGMII) must still be connected to the correct supply rail with the appropriate decoupling capacitance applied. The EMI/Noise filter is not required when this interface is not utilized.”If EMIF filter is not required, why decoupling capacitors still required? This pin is still subject to noise and voltage variation, the filter reduces the AC ripple on the power line. Removing the decoupling capacitors would increase the AC ripple and voltage tolerance beyond acceptable limits – we do not recommend nor at this point in time warranty devices where the decoupling capacitors have been removed. 3. Power a) TI DSP only requires power variation range, no matter the variation is caused by ripple, noise or anything else. b) Does not need to be c